`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:16:42 11/07/2012 
// Design Name: 
// Module Name:    DOWN_SAMPLE_BLOCK 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DOWN_SAMPLE_BLOCK #(parameter LOG_RATE=3, RATE=8, WIDTH=16)
(
	 input clk,
	 input rst,
    input signed [WIDTH-1:0] data_in_r,
    output signed[WIDTH-1:0] data_out_r,
	 input signed [WIDTH-1:0] data_in_i,
    output signed[WIDTH-1:0] data_out_i
    );
	 
	 DN_SAMPLE_UNIT #(LOG_RATE, RATE, WIDTH) U_r
	(
	 .clk(clk),
	 .rst(rst),
    .data_in(data_in_r),
    .data_out(data_out_r)
	 );
	 
	 DN_SAMPLE_UNIT #(LOG_RATE, RATE, WIDTH) U_i
	(
	 .clk(clk),
	 .rst(rst),
    .data_in(data_in_i),
    .data_out(data_out_i)
	 );


endmodule
